Electronics are an integral part of modern life as they are included in personal portable devices such as cellular phones, digital cameras, and music players as well as computers, automobiles, and manufacturing systems. The market for electronic devices or products demand increasing functions and decreasing costs to provide higher performance is smaller sizes.
The electronic industry continues to seek products that are lighter, faster, smaller, multi-functional, highly reliable, and lower in cost. In efforts to meet such requirements, improvements have been attempted in all aspects of electronic development.
Demands for smaller, higher performance integrated circuit devices have motivated development of new techniques for producing smaller and less expensive semiconductor chips. Unfortunately, this development is still not enough to satisfy the demands. Other efforts involve packaging the integrated circuit chip in as small a form factor as possible.
Integrated circuit packaging technology has been driven towards increasing the circuit density on a printed circuit board (PCB) or substrate including the reduction in the number of components needed for a product. The resulting packaging designs are more compact in the physical size, shape, and significantly increase overall circuit density. However, circuit density continues to be limited by the area available for mounting chips.
To condense the packaging of individual chips, packages have been developed in which more than one chip can be packaged at one time for each package site. Each package site is a structure that provides mechanical support for the individual integrated circuit chips. It also provides one or more layers of interconnect lines that enable the chips to be connected electrically to surrounding circuitry.
Attempts to provide multi chip packages have been plagued with manufacturing problems. One problem is special mold processes such as top center gate or side mold gate that can cause warpage and limit package sizes or heights. Another problem is additional substrate treatments for connectors to the substrate. These and other manufacturing problems increase complexity and cost reducing usable packages and rising prices.
Despite the advantages of recent developments in semiconductor fabrication and packaging techniques, there is a continuing need for improving packaging methods, systems, and designs.
Thus, a need still remains for an integrated circuit package system with improved cost, reliability particularly for low pin count, high-density mini QFN devices.
In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems.
Additionally, the need to save costs, improve efficiencies and performance, and meet competitive pressures, adds an even greater urgency to the critical necessity for finding answers to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.